Formal Verification Engineer Fastwater Staffing

WHAT YOU'LL DO

• Define comprehensive formal verification plans, strategies, and methods for a high-quality verification sign-off
• Review and aid in developing the RTL design architecture and specification
• Prove functional correctness of design features using formal verification methods like model checking, logical equivalence checking, or theorem proving
• Formal sign-off delivering high quality IP or block in conjunction with simulation-based methodology for overall verification closure
• Develop and maintain regressions, tools, infrastructure, and integrated formal and functional verification methodology

• Degree in Electrical, Computer Science, Computer Engineering or equivalent experience
• 5+ years of work experience in verifying complex hardware systems using model checking or logical equivalence checking formal methods
• Experience with interactive theorem proving is a plus
• Solid programming skills in Verilog, System Verilog, SVA or PSL, and any scripting language like Tcl, Python, or Perl
• Proficient in debugging CPU, GPU, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs
• Knowledge of advanced computer architecture and micro-architecture concepts