Design Verification Engineer

Design Verification Engineer

We are seeking a highly skilled Design Verification Engineer to join our SoC verification team. The ideal candidate will have hands‑on experience verifying complex SoCs and high‑speed interfaces, including UCIe, Ethernet MAC/PCS, and PCIe Root‑of‑Trust IPs
. You will play a key role in ensuring functional correctness, protocol compliance, and system‑level robustness of next‑generation silicon.

• Develop and execute comprehensive verification plans for SoC and IP‑level designs
• Build System Verilog/UVM‑based verification environments for complex interfaces and subsystems
• Verify and debug UCIe die‑to‑die interconnects
  , including link training, protocol compliance, and error handling
• Verify Ethernet MAC and PCS layers (1G/10G/25G/100G+), including packet flow, PHY interactions, and corner cases
• Perform verification of PCIe Root‑of‑Trust (RoT) IP (e.g., Rambus), including:
  • Key management and authentication
  • PCIe protocol compliance and security features
• Execute SoC‑level integration verification
  , including interconnects, resets, clocks, power management, and coherency
• Create constrained‑random tests, assertions, and functional coverage
• Analyze simulation failures, root‑cause issues, and work closely with design, architecture, and firmware teams to resolve bugs
• Support regression automation, coverage closure, and tape‑out readiness