Senior UVM Verification

Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

Job Type: Contract

Duration: 6+ Months

Location: Hybrid in Santa Clara, CA

Requirement: 6+ years of relevant experience

We are seeking an experienced Design Verification (DV) Engineer to join our team working on a high-performance DSP ASIC project
. The ideal candidate has strong DV fundamentals, deep experience with UVM/System Verilog
, and the ability to contribute to advanced verification environments, debug complex issues, and drive verification quality at both the block and subsystem levels.

• Develop, enhance, and maintain UVM/System Verilog test benches for DSP ASIC components.
• Add new features to existing verification environments and expand functional coverage.
• Create test plans and test cases based on design specifications and verification goals.
• Perform debugging of test failures, waveform analysis, and root-cause identification.
• Execute regressions
  , analyze results, and work closely with designers to resolve issues.
• Contribute to block-level and subsystem-level verification
  , ensuring verification completeness and quality.
• Participate in verification reviews, coverage analysis, and continuous improvement of the verification infrastructure.

Skills:

• UVM
• ASIC
• Test plan
• Test case
• Regressions
• DSP
• Health, Dental and Vision Insurance
• 401k

Mid-Senior level

Contract

Semiconductor Manufacturing