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SoC Verification Engineer: SystemVerilog/UVM & Testbench
Job in
California, Moniteau County, Missouri, 65018, USA
Listed on 2026-01-02
Listing for:
TSMC - Taiwan Semiconductor Manufacturing Company Limited
Full Time
position Listed on 2026-01-02
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading semiconductor foundry is seeking a Design Verification Engineer to verify products including ARM SOCs and memory subsystems. This role involves developing verification methodologies and test plans using System Verilog and UVM. Ideal candidates will have a Master's degree and strong programming skills in Python and C++. The position is based in California, offering competitive salary and comprehensive benefits.
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