Staff Applications Engineer, HAV Solutions

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years working with FPGAs and ASIC designs, and you know that getting a prototype to boot is rarely about the tool, it is about understanding what the design is actually doing. You have debugged partitioning failures, chased down clock domain issues, and figured out why a DDR interface works in simulation but fails on hardware. You do not just follow runbooks.

You understand the flow well enough to know when something does not look right and how to dig deeper.

You are comfortable talking to customer engineering teams about their designs, asking the right questions to understand what they are building, and translating that into a working Proto Compiler flow. When something breaks, you can work through logs, timing reports, and RTL to figure out what went wrong and explain it in a way that makes sense. You have worked with interface IP like PCIe, DDR, Ethernet, or AXI, and you understand how these subsystems behave in a prototype versus simulation.

At Synopsys, you will support customers deploying HAPS and Proto Compiler on real SoC designs. The problems are technical, the customers are smart, and the work you do directly impacts whether their hardware brings up on schedule or slips by months.

• Support customer deployments of HAPS and Proto Compiler, working through the ASIC-to-FPGA flow including partitioning, synthesis, place-and-route, timing closure, and hardware bring-up
• Debug customer designs involving interface IP such as DDR4/DDR5, LPDDR, PCIe, Ethernet, USB, AXI, and other standard protocols
• Reproduce and analyze technical issues reported by customers, working with R&D to identify root causes and deliver solutions or workarounds
• Develop and document methodologies for partitioning strategies, clock architecture, debug instrumentation, and bring-up procedures
• Collaborate with Sales and Customer Success teams to support technical evaluations, proof-of-concept engagements, and deployment planning
• Use Verdi, Proto Compiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues

• Help customers get their prototypes running so they can start software development and system validation weeks or months earlier
• Solve technical problems that unblock critical customer milestones and keep their chip schedules on track
• Provide feedback to R&D that improves Proto Compiler features, usability, and robustness based on real customer use cases
• Build reusable methodologies and documentation that help other applications engineers and customers deploy faster
• Support competitive evaluations where your technical depth and problem-solving ability directly influence customer decisions
• Contribute to the success of SoC programs across AI, automotive, networking, and mobile markets by enabling faster hardware availability

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
• 5-8 years in FPGA implementation, ASIC design, ASIC verification, FPGA prototyping, or applications engineering
• Solid experience with FPGA synthesis, place-and-route, and timing closure using Xilinx Vivado, Intel Quartus, or similar tools
• Working knowledge of System Verilog, RTL design, and verification concepts
• Hands-on experience with at least one interface IP family such as PCIe, DDR, Ethernet, USB, or AXI
• Scripting ability in Tcl, Python, or shell for automation and flow customization
• Experience with Synopsys HAPS, Proto Compiler, or other FPGA-based prototyping platforms is a strong plus

• You can look at a customer's partitioning result and spot the issues that will cause problems downstream before they waste days on place-and-route
• When a customer says their design does not work, you ask specific questions to narrow down whether it is an RTL issue, a tool issue, a constraint issue, or a hardware issue
• You are comfortable working with incomplete information and figuring out what you need to know to move forward
• You can explain a technical problem to a customer…