Principal DSP SW Engineer

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

• Lead the DSP software and firmware architecture for the 5G  physical layer (PHY) for satellite non-terrestrial networks (NTN), define subsystem boundaries and interfaces, and guide hardware/software partitioning with ASIC and system architects while remaining hands‑on in critical implementation work.
• Set the PHY/link‑level modeling and performance‑validation approach across subsystems. Establish representative NTN scenarios, performance and power budgets, and acceptance criteria, and resolve architecture tradeoffs using simulation and implementation evidence.
• Guide the firmware architecture for real‑time processing, memory, data movement, and accelerator control. Co‑design low‑power operation with ASIC architects, including hardware/software partitioning and power‑state coordination; implement or optimize critical functions and resolve performance, power, or integration issues spanning multiple subsystems.
• Establish consistent reference‑model, fixed‑point, and test‑vector practices across the modem PHY, enabling ASIC design and verification teams to trace requirements to expected behavior and reproduce discrepancies.
• Contribute to SystemC transaction-level modeling (TLM) and high‑level synthesis (HLS) development, including synthesizable implementations, with guidance from engineers experienced in these flows.
• Lead DSP software and model contributions to pre‑silicon verification and first‑silicon bring‑up across subsystems. Identify integration risks, agree validation priorities with design and verification leads, and drive resolution of issues spanning algorithms, firmware, and hardware.
• Lead cross‑team technical decisions and architecture reviews, mentor engineers across seniority levels, and guide implementation sequencing and dependency resolution through prototype, tapeout, and silicon validation.

• Demonstrated depth in communication DSP and modem architecture, with a record of resolving difficult performance and implementation tradeoffs across interacting PHY subsystems.
• Ability to implement and debug numerical algorithms in C/C++, and to use Python or MATLAB for simulation, analysis, and test automation.
• Deep practical knowledge of 5G  implementation and relevant 3
  
  GPP specifications, with the ability to assess NTN requirements and translate them into coherent architecture, interfaces, and validation criteria.
• Demonstrated experience converting floating‑point algorithms to fixed‑point implementations, selecting numerical precision, and validating performance against a reference model.
• Demonstrated ability to architect and deliver embedded modem software across programmable processors and hardware accelerators, supported by hands‑on implementation, optimization, and integration work. Experience guiding low‑power ASIC/firmware co‑design, allocating power budgets, and evaluating architecture tradeoffs against power estimates and hardware measurements.
• Ability to build reproducible tests, use version control, document technical assumptions…