Senior ASIC Design Engineer at Celero

Lead the development of ASIC solutions at Celero Communications as a Senior ASIC Design Engineer. Bring your strong DSP and Ser Des expertise to foster groundbreaking technology advancements in optical systems.

Celero Communications is seeking a Senior ASIC Design Engineer who can significantly contribute to cutting-edge ASIC projects targeting high-speed optical communication. With a minimum of 5 years’ experience in digital ASIC design, candidates will need to excel in Verilog, DSP, and cross-functional team collaboration.

This role offers a chance to take ownership of complex designs and drive projects through to silicon implementation.

Key Responsibilities:

• Design high-performance digital circuits in ASICs

• Work on DSP and high-speed Ser Des functionalities

• Collaborate on mixed-signal ASIC integration

• Optimize design performance, power, and area

• Lead verification and integration processes

Requirements:

• Bachelor's degree in Electrical Engineering or similar

• 5+ years experience in ASIC design

• Proficiency in Verilog/System Verilog

• Strong background in DSP techniques

• Familiarity with mixed-signal and analog design

Join Celero to leverage your expertise and influence the future of optical communication technology.
#J-18808-Ljbffr