Principal SerDes System​/DSP Design Engineer

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. We’re building the next generation of 448G electrical Ser Des and pioneering optical IMDD systems to power tomorrow’s networks.

Our engineering team lives at the intersection of high-performance DSP design, system modeling, and optical innovation.
How You Will Contribue:
Lead the design and development of electrical Ser Des DSP architectures for high-speed data communication systems.
Perform system-level evaluation, modeling, and performance analysis of Ser Des transceiver solutions including impairments and mitigation techniques.
Develop algorithms and architectures for adaptive equalization, maximum likelihood sequence detection (MLSD), and timing recovery algorithms.
Integrate control theory and advanced DSP designs into feasible hardware implementations.
Collaborate with cross-functional teams (analog design, ASIC design, electro-optical hardware, firmware) to optimize Ser Des performance in end-to-end systems.
Conduct design trade-offs to meet stringent performance, power, and area targets.
Analyze channel models, analog circuits impairments (DAC, ADC, AFE, …) and system constraints to determine system level margin and FEC (forward error correction) performance and optimize system margin.
Provide system level specifications for different sub-blocks of Ser Des transceivers such as DAC, ADC, AFE, PLL.
Evaluate and model IMDD optical links and formulate strategies to enhance system robustness.
Document design specifications, system performance results, and contribute to IP generation and innovation roadmaps.
Must Haves   Advanced expertise in electrical Ser Des DSP design and implementation.
Proven experience in Ser Des system-level evaluation, modeling, and simulation.
Strong proficiency in control theory and digital signal processing (DSP) applied to high-speed communication systems.
Familiarity with optical IMDD (Intensity Modulation Direct Detection) systems.
Deep understanding of adaptive equalization techniques for high-speed links.
Proficiency with maximum likelihood sequence detection (MLSD) approaches.
Expertise in timing recovery schemes in high-speed serial links.
Practical knowledge of FEC performance modeling and system-level performance optimization.

Experience with MATLAB, Python, or C/C++ for algorithm design and simulation.
Strong problem-solving skills and ability to work across hardware/software boundaries.
Ph.D. in Electrical Engineering with background in digital communications and signal processing.
8+ years of experience in high-speed serial link or communication system design.
Nice to Haves   Knowledge of industry standards such as PCIe, IEEE, Ethernet, or OIF standards for optical communication.
Hands‑on experience with lab bring‑up, characterization, and debugging of Ser Des links.
Pay Range:
The annual salary range is $126,100 - $201,500 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.
In addition to competitive compensation, Ciena…