Design Verification Technical Lead

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THE ROLE:

This is a Technical Lead/Manager role for ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP) in AMD. The primary focus of this role is to Lead and Manage the team responsible for Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC’s. The preferred candidate will also have proven experience in Firmware based HW verification and the ability to contribute to Firmware development initiatives.

These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc.

THE PERSON:
The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.

KEY RESPONSIBILITIES:

Lead a high-performance engineering team

Form a team and nurture talent

Lead team, meet schedule commitments and provide strong support to customers

Collaborate with multi-functional leaders to drive AMD's success

Responsible to performance review , career development for team member .

Managed the team that is responsible for implementing / executing below task

Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.

Hardware/Firmware co-verification in FPGA hardware prototype platform.

Develop and maintain subsystem verification architecture, testbench, test methodology for

Embedded CPU and subcomponent IPs with

AXI/AHB busses and HW accelerators such as

Cryptography, Data Compression, DMA, etc.

Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model

Create abstracted FW and HW performance models

Develop critical target code to collect IP performance key parameters

Explore subsystem architecture performance trade-off for FW and HW optimization

Drive team to Develop and execute subsystem and block level test plans

Develop FW/HW co-verification methodology

Develop UVC and System Response models

Develop and debug UVM and C-DPI test cases with integrated FW

Improve verification metrics

Further develop subsystem and block level test benches using UVM randomized test methodology and C-DPI directed test methodology.

Develop and maintain subsystem level integration scripts

Develop and maintain subsystem testbench build and test run scripts

Drive to verification metrics closure

Interface with SoC integration and SoC DV teams

Define and develop IP level DV API to support SoC level DV effort

Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.

Support SoC level IP emulation, silicon bring-up and debugging effort

PREFERRED EXPERIENCE:

A strong leader with experience working with a distributed team

Strong mentoring and coaching skills

Proven experience managing and leading engineering teams

Prior experience in optimizing performance (client, server, system, or embedded)

Strong system and software engineering background

Strong communications skills. Able to summarize complex problems for executives as well as drill…