Analog SerDes Design Engineer

Position: Staff Analog SerDes Design Engineer
Design transistor-level analog circuits for high-speed Ser Des PHY IP at Synopsys, applying CMOS expertise and simulation methods to silicon-ready results.
This Staff Engineer role serves an experienced engineering professional with semiconductor design and delivery experience. You will develop SoC, ASIC, and Silicon IP solutions while collaborating with engineers, managers, customers, and layout teams. The work covers circuit architecture, verification, modeling, documentation, and technical guidance.

Key Responsibilities:

Design analog and mixed-signal Ser Des PHY circuits
Analyze performance, power, noise, jitter, and reliability tradeoffs
Run PVT, aging, EMIR/SHE, and Monte Carlo simulations
Validate circuit and Verilog-A simulation models
Review layout and lead technical design reviews
Requirements:
Bachelor’s degree with five years’ relevant experience
Master’s degree with minimum three years’ relevant experience
Deep transistor-level CMOS circuit design familiarity
Understanding of SPICE simulation and layout effects
Knowledge of Verilog-A behavioral modeling
Bring transistor-level design, Ser Des circuit expertise, and technical leadership to Synopsys Silicon IP development.