FPGA Verification Engineer

The FPGA Verification Engineer will be responsible for verifying FPGA designs using advanced methodologies and tools.

This role requires strong expertise in System Verilog, UVM, and industry-standard verification tools, along with excellent debugging and problem-solving skills.

The engineer will work independently on complex verification tasks and collaborate with cross-functional teams to ensure high-quality deliverables.

• Develop and execute verification plans for FPGA designs using System Verilog and UVM methodology.
• Utilize industry-standard verification tools such as Questa Sim and Synopsys VCS for simulation and analysis.
• Perform code coverage and functional coverage analysis to ensure completeness of verification.
• Debug and resolve design and verification issues efficiently.
• Automate verification tasks and create scripts for reporting and process optimization.
• Collaborate with design teams to ensure compliance with functional specifications and design guidelines.
• Document verification processes, results, and best practices.
• Participate in technical discussions, reviews, and contribute to process improvements.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of FPGA design principles and architectures.
• Proficiency in System Verilog, UVM, and scripting languages (Python, Perl).
• Experience with hardware description languages such as VHDL and Verilog.
• Hands‑on experience with EDA tools from Cadence, Synopsys, or Mentor Graphics.
• Excellent debugging, analytical, and problem‑solving skills.
• Strong communication and collaboration abilities.

• Familiarity with bus protocols (e.g., AXI, PCIe, USB, Ethernet).
• Knowledge of advanced verification techniques and coverage‑driven methodologies.
• Exposure to physical design, DFT, or mixed‑signal verification concepts.