FPGA Verification Engineer - UVM​/SystemVerilog Pro

A leading engineering firm based in Mountain View, CA is seeking an FPGA Verification Engineer. The candidate must have over 8 years of experience in FPGA, along with proficiency in UVM and System Verilog. This mid-senior level position requires strong problem-solving skills and knowledge of verification tools. The role offers a contract position in a collaborative environment with onsite requirements.
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