Senior Engineer, PCBA DFM

Define and execute Google's long-term technology roadmaps for PCBA assembly, including qualifying advanced, high-density component packaging for future product generations.

Author, standardize, and maintain Google’s proprietary PCBA Design Guidelines for rigid and rigid-flex assemblies, setting the benchmark for hardware manufacturability.

Lead the technical gatekeeping and execution of the OK2

FAB layout approval workflow, conducting critical, high-risk CAD layout reviews to mitigate manufacturing risks before fabrication.

Serve as the engineer, who is directly responsible for high-stakes SMT defect investigations, applying analytical lab techniques to resolve complex assembly failures and recover factory yields during NPI and mass-production ramps.

Define engineering standards for panel array designs, panelization routing clearances, allowable x-out thresholds, and SMT process traceability parameters.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in high-density consumer hardware design, Printed Circuit Board Assembly (PCBA), and Design for Manufacturability (DFM).Experience in Surface Mount Technology (SMT) process integration, high-risk CAD layout reviews, and conducting component-level failure analysis.

Preferred qualifications:

Master's degree or PhD in Materials Science, Mechanical Engineering, or a related technical field.

Advanced understanding of solder metallurgy, intermetallic compound formation, SAC
305/405 properties, and low-temperature solders.

Demonstrated industry leadership through patents, published technical papers, or active contributions to industry standards  part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Senior Design for Manufacturability (DfM)/Surface Mount Technology (SMT) Engineer, you will serve as the principal technical authority for Printed Circuit Board Assembly (PCBA) DfM across Google’s entire consumer hardware portfolio including Phones, Watches, Hearables, and more. In this role, you will bridge the gap between product design and mass production. You will own the technical roadmap for SMT process integration, qualify next-generation component technologies, and lead high-stakes failure analysis task forces during product ramps.

Operating with high technical autonomy, you will influence product design teams early in the development lifecycle and partner directly with global tier-one contract manufacturers to ensure our hardware is built reliably and efficiently at a massive scale.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $144000 - $208000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits helor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in high-density consumer hardware design, Printed Circuit Board Assembly (PCBA), and Design for Manufacturability (DFM).Experience in Surface Mount Technology (SMT) process integration, high-risk CAD layout reviews, and conducting component-level failure analysis.