Rust SW-Silicon Co-verification Engineer

What MatX Is Building

MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. We build custom silicon for training and running the world's largest AI models, with hardware/software co-design across ISA, RTL, simulator, compiler, and kernels.

What You'll Do Here We aim for zero hardware bugs in our chips. A bad bug can cost us millions of dollars, so we invest heavily in correctness. You'll be part of this  addition to the hardware design for our chip ("the RTL"), we have a cycle-accurate microarchitectural simulator ("the sim," written in Rust) created from the same spec by a different  this role, you will perform differential testing between the RTL and the sim: generate inputs, check that the RTL and sim agree with each other, and, when possible, check that they both agree with properties guaranteed by the spec.

You'll also do performance work on the sim itself and on technologies for simulating RTL.Challenges You'll Face The chip's state space is enormous, and sampling interesting points from it is difficult.

A randomly generated sequence of events might find a behavior difference after hundreds of thousands of cycles, and it might be difficult to explain to a human why the RTL and sim diverged; shrinking these test cases down to something minimal is important for human comprehension.

Simulating a large chip is slow. Optimizing the simulators and finding the right subset of the chip to simulate are both important to manage this.

Who You Are Strong Rust experience.

Experience optimizing native code.

Experience with property testing, fuzzing, or similar technologies. Proptest, Hypothesis, Hedgehog, Quick Check, Small Check, Quick Chick, AFL(++), lib Fuzzer, etc.

Experience being responsible for the correctness of real-world systems. You should have been responsible for a system where correctness mattered, and have experience catching bugs before they hit prod and stopping them from recurring.

Bonus Points If You Have

Experience with Bluespec, Haskell, or Verilog. Our RTL code is written in Bluespec Classic (which is mutually intelligible with Haskell) and Verilog. Understanding this code is important for this role, and we'll teach you to read it; if you already know these languages, you'll have a head start.

Experience with microarchitecture. This could be working with ASICs or FPGAs, optimizing code for a particular CPU, or even writing a cycle-accurate simulator for another system (e.g. a game system).

Experience with design verification for hardware. This role complements traditional design verification; if you've done that, the experience is directly applicable.

Experience with formal verification, for software or hardware. Kani, Verus, ACL2, Agda, Lean, Isabelle, Rocq, Alloy, TLA+, Jasper Gold, etc. You won't be working directly with these technologies (a separate team does that), but more experience thinking about properties and the best ways to check them will always be helpful. Experience here will also make working with that team easier.

Experience with search and optimization. Intuitions about searching and pruning large search spaces, learning grammars of inputs and states, evolutionary algorithms, etc. are useful for this role.

Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job-related skills, and relevant education and training. Career length is only a guideline for compensation.

Early Career - $160,000 - $275,000 + equity

Mid Career - $175,000 - $400,000 + equity

Senior Career - $250,000 - $600,000 + equity

What We Offer Time off: 4 weeks PTO (accrued) + 12 company Holidays + up to 3 weeks…