Senior DFT Architect -Gen ASICs
Listed on 2026-11-04
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Engineering
Hardware Engineer, Systems Engineer, Test Engineer, Electronics Engineer
Normal Computing is in search of a seasoned Design-for-Test (DFT) Engineer to own the architecture for our next-generation ASICs, spanning RTL, synthesis, and tapeout. You will lead scan/ATPG, MBIST, boundary-scan, and test-access strategies while collaborating with RTL, verification, physical design, and silicon product engineering teams.
This hands-on leadership role requires establishing scalable DFT flows, guiding external partners, and ensuring manufacturing test readiness from day one.
Join us at Normal Computing Corp. as our next Senior DFT Architect for Next-Gen ASICs in Mountain View, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior DFT Architect for Next-Gen ASICs role in the description above.
We appreciate your interest in this position.
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