Senior DFT Engineer: ASIC Test & Silicon
Listed on 2026-11-04
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer
Normal Computing is seeking a Design-for-Test (DFT) Engineer to own DFT architecture for next-generation ASICs, driving scan/ATPG, MBIST, and boundary-scan strategies from RTL through tapeout and silicon bring-up.
You will collaborate with RTL, verification, physical design, and silicon product engineering teams, establishing scalable DFT flows and partnering with external partners to deliver production-ready test patterns and collateral. Strong leadership and scripting skills are essential.
Our organisation is growing, and we are hiring a Senior DFT Engineer: ASIC Test & Silicon Bring-Up in Mountain View, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 140..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior DFT Engineer: ASIC Test & Silicon Bring-Up role in the description above.
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