Senior ASIC Physical Design Engineer – PPA & Tapeout
Listed on 2026-11-04
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Engineering
Hardware Engineer, Electronics Engineer, Electrical Engineering, Systems Engineer
MatX Inc. in Mountain View, CA, is seeking silicon physical design engineers to develop high-performance, power-efficient silicon for GenAI. You will own subsystems and drive PD from RTL to tapeout, ensuring scalable, correct implementations.
The role requires BS in Electrical Engineering and 8+ years of ASIC PD experience, with strong Python/TCL/Perl skills and collaboration with Design/DFT teams to optimize performance, power, and area.
Our team is growing, and we are hiring a Senior ASIC Physical Design Engineer – PPA & Tapeout in Mountain View, CA, United States.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC Physical Design Engineer – PPA & Tapeout role in the description above.
We appreciate your interest in this position.
Join MatX Inc. and contribute to our ongoing work.
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