Design Verification Engineer – AI-Driven ASICs & Tapeout
Listed on 2026-11-05
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Engineering
Test Engineer, Electronics Engineer
Normal Computing, based in Mountain View, is seeking a Design Verification Engineer to verify AI-enabled ASICs and raise the bar for verification flows. You will work on thermodynamic ASIC verification, testbench environments, and coverage to tapeout, applying advanced DV techniques.
The ideal candidate has 5+ years in digital verification at a semiconductor or EDA company, deep System Verilog/UVM expertise, and hands-on experience with vManager, Xcelium, and Jasper, plus Python or Perl
We are currently recruiting a Design Verification Engineer – AI-Driven ASICs & Tapeout for our team in Mountain View, CA, United States.
As a Design Verification Engineer – AI-Driven ASICs & Tapeout, you will play an important part at Normal Computing Corp. in Mountain View, CA, United States.
We invite applications for the Design Verification Engineer – AI-Driven ASICs & Tapeout position located in Mountain View, CA, United States.
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