RTL Design Engineer

Job Description:

Wipro Limited is a leading technology services and consulting company dedicated to delivering innovative solutions for complex digital transformation needs. With a global presence and a workforce of over 230,000, Wipro aims to help clients build sustainable businesses and thrive in a dynamic environment.

Responsibilities:

• Deliver successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• Engage in Digital Design including RTL coding in Verilog/System Verilog, and manage RTL2PD tool/flow setup, maintenance, and debugging.
• Collaborate with Physical Design (PD) engineers to optimize performance, area, and power constraints based on micro-architecture understanding.
• Design complex control logics on Network-On-Chip ASICs.

Qualifications:

• 9 years of related technical engineering experience, or a Bachelor's degree in a relevant field with 6 years of experience, or a Master's degree with 4 years of experience.
• 8 years of experience in ASIC/SOC design, particularly in arbitration and fabric logics.
• Track record of successful ASIC tape outs in deep sub-micron technologies.

Skills:

• Strong understanding of physical design impacts on micro-architecture.
• Experience with complex control paths, memory hierarchies, and industry-standard interfaces like AXI.
• Excellent communication skills and ability to facilitate collaboration.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Work Email

Free No obligation Response within 24 hours