Job Description & How to Apply Below
Company
Description:
Curvia AI is a technology and AI solutions company that transforms complexity into opportunity through enterprise solutions, AI-powered automation, and data-driven insights. We build practical, scalable, and human-centered technology grounded in integrity, security, and responsible innovation.
Role Overview :
We are seeking a KiCad Task Executor with practical experience in electronic design automation, schematic capture, and multi-layer PCB layout. The role involves executing complex hardware-design tasks, recording human reference demonstrations, validating task solvability, identifying electrical edge cases, and testing automated grading rules.
Offer details:
Mode of work:
Fully Remote
Employment Type:
Contract
Commitments
Required:
Full-time. 40 hours per week with at least 4 hours PST overlap
Start Date:
Immediate
Number of openings: 10
Pay: US $15/task (AHT 1 hour)
Years of
Experience:
3+ years
Target Applications and Toolchain
KiCad, Eeschema, Pcbnew, Gerber, Design Rule Check (DRC), and the KiCad Python API.
Job Requirements:
Practical hands-on experience with KiCad for schematic capture and multi-layer PCB routing.
Strong knowledge of PCB layouts, schematic wiring, footprints, symbols, routing, and DRC error resolution.
Ability to navigate EDA tools efficiently and apply routing best practices.
High attention to pin assignments, component orientation, and clearance constraints.
Clear written English for submitting bug reports and execution feedback.
Experience working in remote Linux desktop environments, including noVNC or VNC is preferred
Experience in PCB layout review, hardware testing, or EDA benchmarking is preferred.
Job Responsibilities:
Complete multi-step schematic-wiring and PCB trace-routing tasks in remote Ubuntu/Linux desktop environments.
Record clean human execution trajectories, including keystrokes, mouse-routing actions, footprint placement, and DRC runs.
Identify ambiguous electrical specifications, missing footprints, clearance conflicts, and software-interface issues.
Route PCBs and wire schematics using alternative valid design paths to verify accurate automated grading.
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