Snr Digital Design Engineer

Senior Digital Design Engineer

At Allegro Micro Systems we seek an experienced engineer to define and implement digital architecture for our advanced motor drive ICs.

• Lead the definition of system‑level requirements and own the digital architecture for both IP‑level and full System‑on‑Chip (SoC) designs.
• Architect and implement reusable RTL modules, driving top‑level chip integration across the entire digital flow with an emphasis on low‑power and high‑performance design.
• Contribute to the evolution of digital design methodology, evaluating and deploying new tools and best practices to improve efficiency and quality.
• Collaborate on FPGA validation, pre‑silicon emulation, and robust verification of the entire system, ensuring a seamless hardware/software interface.
• Partner with verification to define success criteria and achieve comprehensive functional coverage for first‑pass silicon.
• Work with the physical implementation team to resolve critical timing, power, and area challenges on advanced technology nodes.
• Mentor junior engineers and serve as a technical partner to systems, software, test teams, customers, and EDA vendors.

• PhD or Master’s degree in Electronics or a related field (or equivalent experience).
• 6+ years of senior digital design or architecture experience, with a track record in complex algorithmic IP and full SoC design (CPU subsystems, interconnect fabrics such as AMBA/AXI, system protocols).
• Demonstrated success designing and implementing complex digital IP and contributing to SoC integration from specification to tape‑out and silicon validation.
• Strong command of advanced digital design principles, including low‑power and high‑speed techniques.
• Solid understanding and practical application of advanced DFT/DFM techniques (scan compression, BIST) and FPGA/emulation for complex systems.
• Excellent verbal and written communication skills and the ability to present complex technical concepts to diverse audiences.
• Experience mentoring and collaborating with junior engineers.

• Expertise with Cadence or equivalent EDA toolsets for the entire front‑end design flow.
• Experience with functional safety standards such as ISO
  26262.

Up to 10–20% domestic and international travel to support customers, vendors, and off‑site design teams.