Senior Application Engineer - Digital Design Verification; -TPEN

Math Works has a hybrid work model that enables staff members to split their time between office and home. The hybrid model provides the advantage of having both in-person time with colleagues and flexible at-home life optimizations. Learn More:

We are seeking a talented Senior Digital Design Verification Engineer with expertise in ASIC/SoC verification and hardware development. The ideal candidate will have hands‑on experience with DPIC, UVM, System Verilog, and Verilog/VHDL for FPGA and SoC design, as well as familiarity with Simulink and MATLAB.

Math Works nurtures growth, appreciates diversity, encourages initiative, values teamwork, shares success, and rewards excellence.

• Serve as a technical member of the sales team, engaging with prospective customers to generate excitement and establish confidence in Model-Based Design solutions.
• Demonstrate the value of Math Works' MATLAB, Simulink, and HDL Code Generation products for deploying and verifying complex algorithms on FPGA and SoC platforms.
• Collaborate directly with customers to develop project roadmaps and technical procedures for successful Model-Based Design deployments and verification, supporting revenue growth.
• Define deployment requirements and partner with development engineers to implement new features or optimize existing ones, ensuring clear communication of product value.
• Develop technical procedures to streamline the rollout of solutions that address complex deployment challenges.
• Occasional travel (air and ground) for customer presentations and planning discussions as needed.
• Work closely with sales teams and other customer‑facing staff in a fast‑paced, evolving environment.

• Master's degree in Engineering or Computer Science strongly preferred.
• Experience using MATLAB and Simulink for FPGA, ASIC, and SoC design verification or hardware development.
• Proficiency in DPI-C, UVM, System Verilog, and MATLAB, with strong verification skills.
• Experience with verification EDA tools from Cadence, Synopsys, Siemens, or AMD.
• Background in signal processing development for FPGA, ASIC, or embedded processor targets.
• Knowledge of simulation applications, synthesis and implementation tools, and performance trade‑offs (resources, processing speed, power).
• Strong customer focus and ability to translate customer needs into actionable plans for Math Works solutions.
• Excellent verbal and written communication skills.
• Flexibility to manage multiple projects and adapt to changing business opportunities and external demands.
• US Citizenship preferred due to customer requirements, but not mandatory.

• Experience with fixed‑point development.
• Background in advanced RADAR, signal/image processing, wireless communications, or control applications.
• Experience with automatic code generation tools.
• Tools development experience.
• Extensive experience with MATLAB or Simulink.
• Prior customer‑facing experience.

• FPGA's
• ASICs
• MATLAB
• A bachelor's degree and 6 years of professional work experience (or a master's degree and 3 years of professional work experience, or a PhD degree, or equivalent experience) is required.

The Math Works, Inc. is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. The EEO is the Law poster is available here. Math Works participates in E-Verify. View the E-Verify posters here.