PIC Physical Design & Layout Engineer

Overview

We are looking for a PIC Physical Design & Layout Engineer to design and prepare photonic integrated circuits for manufacturing on a thin-film lithium niobate (TFLN) platform.

You will own the physical design, layout, and tapeout of internal and customer chips, ensuring compliance with PDK rules, fabrication constraints, and packaging and test requirements. You will work closely with simulation, PDK, fabrication, and measurement teams across the full production flow.

• Design and integrate full-chip PIC layouts.
• Perform DRC/LVS, tapeout, and design sign-off.
• Generate production-ready GDS and mask data.
• Apply and contribute to PDK rules and design flows.
• Align layouts with packaging, test, and manufacturing needs.

• MSc or PhD in Photonics, EE, Physics, or related field.
• 3+ years of experience in PIC physical design and layout.
• Strong experience with DRC/LVS and tapeout flows.
• Proficiency with PIC layout tools (IPKISS, GDSFactory, Cadence, L-Edit, or similar).
• Solid understanding of PDKs, layer stacks, and design rules.
• Comfortable with Python or scripting for layout automation.

• Photonic simulation experience.
• Exposure to fabrication, packaging, or PIC characterization.
• Core technical role in a deeptech startup building an industrial PIC platform.
• High ownership, real tapeouts, real production impact.
• Competitive salary, bonus, and ESOP.
• Based in Western Switzerland with flexible hybrid setup.

Send your application to

Subject:

Single PDF including cover letter, CV, and 2 references.

(applications reviewed on a rolling basis)