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Senior UVM Verification Engineer

Job in 2000, Neuchâtel, Neuchâtel, Switzerland
Listing for: Technify Talent
Full Time position
Listed on 2026-08-16
Job specializations:
  • Engineering
    Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 110000 - 160000 CHF Yearly CHF 110000.00 160000.00 YEAR
Job Description & How to Apply Below

An established semiconductor company is looking for a Senior UVM Verification Engineer to play a key role in the verification of advanced ICs for automotive and sensing applications.

This is a high-impact opportunity for a UVM specialist who wants to work beyond traditional block-level verification. You'll take ownership of system-level verification, developing sophisticated System Verilog/UVM environments across complex digital, analog and embedded software functionality.

What you'll do as a Senior UVM Verification Engineer:
  • Lead and execute functional verification activities using System Verilog and UVM for complex semiconductor products.
  • Develop, maintain and enhance UVM-based verification environments, test benches, sequences, monitors, scoreboards and functional coverage.
  • Define verification strategies and plans based on high-level system requirements and digital specifications.
  • Develop high-level functional models and verification components to support system-level and top-level simulation.
  • Perform detailed verification of digital functionality and its interaction with analog/mixed-signal circuitry and embedded software.
  • Identify, investigate and debug complex functional and verification issues across multiple engineering domains.
  • Work closely with system, analog, digital, embedded software and test engineers to ensure comprehensive product verification.
What you'll bring as a Senior UVM Verification Engineer:
  • Master's degree in Electronic Engineering, Microelectronics or a related discipline.
  • 5+ years of experience in verification within the semiconductor / microelectronics industry.
  • Strong, hands-on expertise in System Verilog and UVM, this is a core requirement for the role.
  • Proven experience developing and deploying UVM verification environments and methodologies for complex digital or mixed-signal ICs.
  • Strong understanding of verification concepts including functional coverage, constrained-random verification, assertions, score boarding and reusable verification components.
  • Experience with top-level or system-level verification of complex semiconductor products.
  • Exposure to mixed-signal environments, with an understanding of the interaction between analog, digital and/or embedded software functionality.
  • Ability to translate high-level requirements and specifications into effective verification strategies and test scenarios.
  • Experience debugging complex issues across multiple levels of a semiconductor design.
  • Strong communication skills and the ability to collaborate effectively with system, analog, digital, software and test development teams.
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Position Requirements
10+ Years work experience
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