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Lead Digital Verification Engineer

Job in Mount Royal, Gloucester County, New Jersey, 08061, USA
Listing for: Cadence
Full Time position
Listed on 2025-10-08
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Location: Mount Royal

Join to apply for the Lead Digital Verification Engineer role at Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:
Lead Verification Engineer


Location:
Montreal, Ottawa, Toronto

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

Responsibilities
  • Verification of digital RTL
  • Development of re-usable verification components and environments
  • Contribution to all aspects of digital verification
Requirements Minimum Experience
  • Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
  • Understanding of verification architecture and methodologies
  • Understanding of Metric Driven Verification
  • Understanding of Universal Verification Methodologies
  • Understanding of the identification, planning and creation of functional coverage and checks
  • Understanding of System Verilog Assertions (SVAs)
  • Understanding of digital design flow
Preferred Experience
  • Master of Science in EE/CPE/CSC
  • Experience with System Verilog UVM coding language
  • Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk
  • Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
  • Exposure to Formal Verification Technologies
  • Exposure to Mixed Signal Design experience
  • Experience with Cadence tools experience
  • Exposure to Low Power verification experience using CPF or UPF

Cadence is an equal-opportunity employer committed to hiring a diverse workforce.

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