Senior Principal Verification Engineer

Location: Parkers Landing

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr Principal Digital Verification Engineer

Location:
Montreal, Ottawa, Toronto

Job Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The candidate will primarily be responsible for leading a team of engineers in the verification of digital RTL and development of re-usable verification components and environments.

The successful candidate will be a highly motivated self-starter and with strong leadership qualities.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.

The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.

The candidate should be able to work as part of a focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets.



Job Responsibilities

• Project planning and progress tacking
• Leading team of 5-15 engineers in the execution of verification tasks
• Definition and Management of Verification Plans (vPlans) using Cadence vManager tools
• Architecture of Verification Environments for complex IP such Multi-protocols PHY
• Development of UVM-SV Scoreboards for self-checking regressions
• Development of Functional Coverage as part of Metric Driven Verification Environments
• Development of System Verilog Assertions for use in Formal and Simulation Environments
• Creation and Management of Automated Regression Environments, e.g. Jenkins
• Participation in Technical Review Meetings and Checklist Reviews
• Close Collaboration with Design Engineers to debug complex test scenarios

Job Qualifications

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
• 12+ years’ experience in microelectronics/EDA industry
• Experience of Verilog RTL Design essential
• Experience of Metric Driven Verification (MDV) essential
• Excellent oral and written English essential
• Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
• Self-motivated with excellent planning, interpersonal, and communication skills

Cadence is an equal-opportunity employer committed to hiring a diverse workforce.

Due to the nature of the role that requires interaction with other entities globally and with employees and stakeholders in other provinces in Canada, knowledge of the English language is required for this position.

Titre:
Concepteur Principal Senior en vérification numérique

Localisation:
Montreal, Ottawa, Toronto

Description

Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.

Le candidat aura la charge de diriger une équipe dans la vérification de modules numériques RTL et du développement de modules de vérification réutilisables

Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élab oration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.

Le candidat devra posséder des connaissances avancées…