Sr. Designer Engineer; ASIC​/FPGA)

Design and develop digital ASICs and FPGAs and/or mixed-signal ASICs for the advanced communications silicon program of a leading commercial space company. You will take designs from HDL implementation through verification, timing and signoff, and support lab integration alongside systems, firmware, architecture and product engineering teams.

Remote. Open to candidates anywhere in the US. If the contract converts to direct employment, you must be local to (or relocate to) one of the client sites in Southern California or Austin, TX. US citizenship required.

• Design and develop digital ASICs and FPGAs and/or mixed-signal ASICs.
• Implement designs in HDL (VHDL, Verilog and/or System Verilog).
• Develop verification methodologies and test benches for block- and system-level verification.
• Create and execute test plans, develop test harnesses and implement coverage models.
• Conduct timing analysis, noise analysis and other signoff checks.
• Collaborate with systems, firmware, architecture and product engineering teams.
• Support lab integration and troubleshooting.
• Resolve timing, congestion and other implementation issues.

• 7+ years of ASIC design and implementation experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering or a related technical discipline.
• FPGA and ASIC design experience.
• Proficiency in HDL (VHDL, Verilog and/or System Verilog).
• Design verification and test bench development experience.

• MS or PhD in Electrical Engineering, Computer Engineering or a related field.
• Full ASIC/FPGA lifecycle experience (architecture, design, simulation, verification, validation, integration and test).
• Software-defined radio architectures, ADC/DAC and/or DSPs.
• DSP and communications systems knowledge: spread spectrum, forward error correction, modulation types (QPSK, QAM, PCM/FM, PAM).
• Strong object-oriented programming and scripting (Python, TCL, Perl).
• Physical design flows and industry-standard EDA tools; RTL-to-GDSII physical design and signoff.
• Deep sub-micron FinFET and CMOS technologies.