Senior ASIC STA Engineer — Timing Chip Mastery

Tensordyne, a Sunnyvale-based AI system solutions company, is seeking a senior ASIC STA lead to drive frontend physical design and timing closure across full-chip and block-level work streams. You will collaborate with a global team, develop scalable STA workflows, and optimize timing with Cadence/Synopsys tools in a fast-paced HPC environment.

Ideal candidates have 10+ years in ASIC design, strong SDC skills for PCIe/Ser Des interfaces, and a track record leading backend teams, while enjoying a

This role, Senior ASIC STA Engineer — Timing & Full-Chip Mastery at Tensordyne, could be your next opportunity.

This posting is for the Senior ASIC STA Engineer — Timing & Full-Chip Mastery role at Tensordyne, based in Sunnyvale, CA, United States.

We are looking to fill the Senior ASIC STA Engineer — Timing & Full-Chip Mastery position at Tensordyne in Sunnyvale, CA, United States.