Senior SERDES Applications Engineer

Role Overview
We are seeking an experienced

Role Overview
We are seeking an experienced Applications Engineer specializing in advanced high-speed Ethernet Ser Des technologies. In this key technical role, you will bridge the gap between silicon architecture, firmware development, hardware qualification, and customer implementation.
You will work closely across cross-functional groups—including ASIC design, manufacturing, test, calibration, and reliability teams—while providing technical leadership and direct customer engagement.

• Direct Customer Interaction:
  Drive direct technical support, debug complex issues, and deliver technical training for customers and Field Application Engineers (FAEs).
• Cross-Functional Collaboration:
  
  Lead hardware/software bring-up efforts in collaboration with ASIC, manufacturing, test, calibration, and reliability engineering teams.
• Project Management:
  Manage multiple complex tasks and project timelines concurrently.

• Schematic & Layout Review:
  Review PCB schematics and board layouts for high-speed signal integrity and hardware compatibility.
• Lab Debug & Measurement:
  Perform hands‑on debugging using Ethernet traffic generators, high‑speed oscilloscopes, jitter analyzers, spectrum analyzers, network analyzers, and OTN testers.

• Degree: BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• Experience:
  
  8–10+ years of practical experience in high-speed hardware, Ser Des, or system/board engineering.

• Ser Des & PHY Expertise:
  Strong working knowledge of high-speed (224
  
  Gbps / 112
  
  Gbps+) PHYs and Ser Des architectures.
• Ethernet & Optical Standards:
  Deep knowledge of 100
  
  Gbps / 200
  
  Gbps / 400
  
  Gbps optical systems and standards; OTN experience is a plus.
• PAM4 Modulation:
  Hands‑on experience with PAM4 signaling and high‑speed Signal Integrity (SI) analysis.
• SoC Architecture:
  Experience in architecture, programming, or support of complex System‑on‑Chip devices.
• Direct experience with MACsec (802.1AE) key management and data‑plane acceleration.
• PTP (IEEE 1588) hardware time stamping / clock recovery synchronization in optical hardware.
• Reliability & Failure Analysis:
  Background driving product qualification, stress testing, reliability investigations, and board‑level failure analysis (FA).

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long‑term growth and success.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:
how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice‑to‑have. It's the critical path.

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon…