SIPI Characterization Engineer

A fast-growing AI hardware company is building high-performance compute systems designed to run large-scale AI workloads as efficiently as possible.

The team develops advanced accelerator silicon and systems, with a strong focus on performance, power efficiency, high-speed connectivity, and scalable hardware infrastructure.

We are looking for a hands-on Signal Integrity, Power Integrity, and Characterization Engineer to own electrical characterization of high-speed Ser Des interfaces and power-delivery networks across advanced accelerator compute systems.

You will build and scale test-automation infrastructure capable of validating thousands of high-speed channels while working closely with signal-integrity, power-integrity, packaging, and board-design engineers.

The role spans lab characterization, automation, design correlation, and feedback into future board, package, and silicon designs.

• Characterize high-speed Ser Des interfaces including PCIe, Ethernet, and custom protocols.
• Perform BER testing, eye-diagram analysis, jitter characterization, link-margin analysis, and PVT characterization.
• Tune and optimize Ser Des transmitter and receiver equalization settings.
• Perform channel characterization including insertion loss, return loss, and crosstalk measurements.
• Use VNA and time-domain reflectometry techniques for electrical channel analysis.
• Develop methodologies to correlate simulation predictions with measured results.
• Drive feedback loops that improve modeling accuracy and future designs.

• Measure and analyze transient noise and dynamic voltage droop on high-current power rails.
• Characterize power-delivery-network impedance across board, package, and silicon.
• Compare measured PDN behavior against target-impedance requirements.
• Identify weaknesses in power-delivery designs.
• Partner with power-delivery and board-design teams to define and validate mitigation strategies.
• Analyze decoupling, resonance behavior, voltage-regulator response, and related power-integrity issues.

• Architect, develop, and maintain scalable electrical-design-validation test infrastructure.
• Automate characterization across large numbers of Ser Des channels in multi-chip accelerator systems.
• Integrate oscilloscopes, BERTs, VNAs, power analyzers, and other lab equipment into automated test flows.
• Develop test automation using Python or similar scripting environments.
• Build data pipelines for test-result collection, statistical analysis, visualization, and rapid triage.
• Improve test coverage and repeatability across complex hardware platforms.

• Partner with signal- and power-integrity engineers on advanced package designs.
• Support characterization of die-to-die interconnects, bump arrays, interposers, and package structures.
• Collaborate with board designers on PCB stackups, routing rules, via optimization, and decoupling strategies.
• Review characterization results and translate findings into actionable design recommendations.
• Influence layout guidelines, design rules, and future board, package, and silicon revisions.

• 5-10 years of industry experience in hardware characterization, signal integrity, power integrity, or related areas.
• Bachelor's degree or higher in Electrical Engineering or a related discipline.
• Deep understanding of high-speed Ser Des architectures and PHY-layer operation.
• Strong knowledge of equalization, jitter decomposition, BER, eye diagrams, and link-margin analysis.
• Strong understanding of transmission-line theory, including:
• Wave propagation
• Impedance matching
• Reflections
• Skin effect
• Dielectric loss
• Strong understanding of power-delivery-network design principles, including:
• Target impedance
• Resonance
• Bypass and decoupling capacitor placement
• Voltage-regulator loop dynamics
• Hands-on proficiency with high-speed electrical lab equipment.
• Experience developing test automation, preferably in Python.
• Ability to correlate simulation and measurement data and communicate findings to design teams.

• AI accelerator or GPU system-validation experience.
• PCIe compliance-testing experience.
• Familiarity with JEDEC methodologies.
• Statistical process control or large-scale silicon-characterization experience.
• PCB layout-review experience.
• Advanced package-design experience.
• Die-to-die or chiplet…