Quantum TSV Integration Engineer

## Quantum TSV Integration Engineer Apply locations:
USA
- New York
- Maltatime type:
Full time posted on:
Posted Yesterday job requisition :
JR-2602349

Global Foundries Fab8 is seeking a highly skilled and motivated R&D TSV engineer to become part of our Quantum Advanced Packaging team. The primary responsibility of this position is to own development and integration of cryogenic, superconducting TSV technologies enabling high-density vertical interconnects for scalable quantum packaging from concept through manufacturing.
** About Global Foundries
** Global Foundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, Global Foundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit
** Job Summary
** Global Foundries Fab8 is seeking a highly skilled and motivated R&D TSV engineer to become part of our Quantum Advanced Packaging team.  The primary responsibility of this position is to own development and integration of cryogenic, superconducting TSV technologies enabling high-density vertical interconnects for scalable quantum packaging from concept through manufacturing.
** Essential Responsibilities
*** Lead development of through-silicon via (TSV) processes for cryogenic and superconducting applications.
* Define TSV architectures including:  + Superconducting liners (e.g., Nb, Al-based)  + Dielectric isolation schemes  + Via geometries (diameter, depth, pitch)
* Ensure TSV designs are optimized for:  + Low-loss electrical/RF signal transport  + Cryogenic thermal and mechanical stability
* Own end-to-end TSV integration flows across:  + Via etch, liner deposition, dielectric, and metallization  + Wafer thinning, reveal, and backside processing  + Integration into 2.5D/3D packaging stacks
* Drive process integration planning to enable prototyping and qualification across programs.
* Develop TSV solutions for superconducting interposers and 3D integration platforms
* Support integration with:  + Bump/interconnect layers  + Redistribution routing layers (RDL)  + Assembly and bonding flows
* Ensure TSVs enable high-density vertical interconnects for quantum system scaling.
* Enable prototype builds and development lots, ensuring smooth execution through fab and assembly flows.
* Support transition from R&D to pilot to manufacturable flows.
* Collaborate with device/test teams to ensure TSVs meet:  + Cryogenic electrical performance requirements (DC + RF/microwave)  + Low resistance and minimal loss for superconducting operation
* Support characterization of:  + Signal integrity (noise, crosstalk)  + Thermal leakage across vias
* Develop strategies to improve:  + TSV yield and process robustness  + Integration reliability under cryogenic conditions
* Identify and analyze failure modes such as:  + Liner defects / discontinuities  + Delamination or cracking during thermal cycling  + Void formation or via integrity issues
* Lead root-cause analysis and corrective actions.
* Work closely with materials teams to:  + Select TSV liner and dielectric materials compatible with superconducting operation  + Understand cryogenic behavior (CTE mismatch, stress, superconductivity limits)
* Optimize interface integrity between via liner, dielectric, and substrate.
* Define requirements for TSV-specific process tools:  + Deep silicon etch (DRIE)  + Conformal deposition (PVD/CVD/ALD)  + Wafer thinning and reveal
* Collaborate with equipment vendors and suppliers to develop new capabilities.
* Support qualification of new tooling and materials.
* Interface across:  + Interconnect (bump / RDL) teams  + Assembly and integration engineers  + Device / qubit / system engineers
* Ensure co-optimization of TSVs with full packaging stack.
* Drive development of next-generation TSV scaling, including:  + Smaller diameters and higher aspect ratios  + Alignment with micro-bump pitch scaling
* Contribute to cryogenic 3

DHI roadmap and APPC capability build-out.
* Evaluate novel via concepts (e.g., superconducting-lined, partially filled, or air-gap vias).
* Generate:  + TSV integration flows and specifications  + Design rules and process documentation
* Provide technical updates, reports, and data-driven insights.
* Contribute to IP, publications, and conference outputs.
** Other…