ASIC & FPGA Design Engineer Stf – E4 Telework

Lockheed Martin is seeking an experienced FPGA Designer to join our Mission Systems team in Owego, NY. This remote telework position emphasizes work-life balance while contributing to innovative advancements in defense and aerospace technology. The role involves leading hardware development for Advanced Processing systems, ensuring technical integrity, and managing stakeholder communications.

Responsibilities:

• Support overall organizational process compliance, including management of the FPGA Development Process.
• Conduct FPGA development activities and provide technical guidance.
• Ensure the technical integrity and completeness of deliverables.
• Manage customer interfaces and coordinate with multiple stakeholders.
• Leverage Digital Transformation tools to enhance development processes.

Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline with approximately nine or more years of relevant experience; or a master’s degree with approximately seven or more years; or equivalent experience.
• Significant FPGA architecture, RTL design, implementation, integration, and verification experience using VHDL, Verilog, or System Verilog.
• Proficiency with AMD/Xilinx Vivado, Intel Quartus, Microchip Libero, or comparable tools.
• Demonstrated ability to solve complex technical problems and lead work with limited direction.
• Demonstrated technical leadership, collaboration, mentoring, and communication skills.
• U.S. citizenship and ability to obtain an Interim Secret clearance before starting and maintain a final Secret clearance.

Skills:

• DO-254 design assurance, traceability, coverage, audits, or certification evidence.
• Experience with AMD/Xilinx FPGA/SoC/ACAP, Polar Fire/Polar Fire SoC, or Intel FPGA.
• Knowledge of PCIe, Ethernet, DDR, JESD
  204, Aurora, SERDES, LVDS, AXI, or source-synchronous interfaces.
• Advanced timing analysis, CDC/RDC, floor planning, pin/bank validation, and timing closure.
• Familiarity with UVM, constrained-random verification, coverage, regression automation, formal methods, or HIL.
• Programming skills in Python, Tcl, MATLAB, C/C++, or similar automation tools.
• Experience with Git, CI/CD, automated builds/regressions, issue tracking, and configuration management.
• FPGA technical-review leadership and multidisciplinary/customer coordination.
• Ability to estimate, schedule, and manage staffing plans, technical risks, and program leadership status.
• Experience in mentoring, knowledge transfer, reuse, and process improvement.