Design Verification Engineer Source FPGA/ASIC
Listed on 2026-10-16
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Engineering
Test Engineer, Hardware Engineer
Location: New York
Hudson River Trading is seeking a Design Verification engineer to join our Hardware team in New York. You will write test benches, verification plans and robust environments for FPGA/ASIC based compute engines used in ultra-low latency trading.
Candidates excel in RTL verification, Python and Linux, with Cocotb familiarity; C++ a plus. You will collaborate with designers, maintain test suites and contribute to open-source tool chains that power our platforms.
As a Design Verification Engineer — Open-Source FPGA/ASIC, you will play an important part at Hudson River Trading in New York, NY, United States.
Learn more about the Design Verification Engineer — Open-Source FPGA/ASIC role in the description above.
We appreciate your interest in this position.
Join Hudson River Trading and contribute to our ongoing work.
Take a moment to read everything above and see whether this role is right for you.
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