RTL Design Engineer — Tapeout- AI ASICs

Normal Computing is seeking an RTL Design Engineer to design and verify the digital logic at the heart of its thermodynamic hardware. You will own RTL from microarchitecture to tapeout, writing synthesizable System Verilog and building verification environments with UVM, cocotb, or formal tools.

You will work closely with architects and physical designers to ensure correctness and realizability. This role blends design and verification, demanding silicon experience and a track record of tapeouts.

We are currently recruiting a RTL Design Engineer — Tapeout-Ready AI ASICs for our team in New York, NY, United States.

We would love to welcome a new RTL Design Engineer — Tapeout-Ready AI ASICs to our team in New York, NY, United States.

For the RTL Design Engineer — Tapeout-Ready AI ASICs position at Normal Computing Corp., we are reviewing applications now.