ASIC​/RTL Design Engineer

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Kenyi Technologies is a early stage startup operating in stealth mode. Kenyi is developing an Infrastructure platform that enables the use of a Cloud Native SW stack at the Edge with appliance-like efficiency. The Kenyi Technologies Founding Team is comprised of ex-Qualcomm engineers with years of experience.

As an ASIC/RTL Design Engineer you will work on developing a Proof-of-Concept that will migrate to an end product. This is an entry to mid-level position and requires a willingness to work within an early stage startup as part of a small team, but with the potential to grow exponentially given longer term objectives. The position requires knowledge of RTL design and verification flows including RTL coding, simulation, synthesis, static timing analysis, scripting, digital circuit design techniques (e.g. clock domain crossing) and verification.

Knowledge of either Networking, DSP or Communication systems is a strong plus for the position.

3 to 5 years of experience in ASIC/RTL design and development. Will consider new grads with strong internship and/or project experience.

• HDL coding (System Verilog preferred)
• Digital design fundamentals (e.g. clock domain crossing, digital arithmetic, memory subsystem)
• RTL Simulation and debugging
• Synthesis
• Static timing analysis
• Linting tools
• Code coverage
• Scripting (e.g. Python, Perl)
• C++
• Lab bringup and debug

• Either Networking, DSP or Communications system design
• UVM based Verification methodology
• Embedded SW experience (e.g. drivers, Linux OS, PCIe)

• Minimum requirement: BS in Electrical or Computer Engineering.
• MS/PhD in Electrical or Computer Engineering a plus.

Entry level

Full-time

• Engineering and Information Technology

• Semiconductor Manufacturing

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