Design Verification Engineer

Formal Verification Engineer – Semiconductor Division

About the role:

I am seeking a highly motivated and detail-oriented Formal Verification Engineer to join an established Verification group in the historic City of Oxford. In this role, you will be responsible for applying formal methods to verify the correctness of complex digital designs. You will work closely with design, simulation, and functional verification teams to ensure product reliability, safety, and compliance with specifications.

• Develop and execute formal verification plans for digital blocks and systems.
• Identify key properties and in variants for verification using formal methods.
• Write formal specifications using System Verilog Assertions (SVA), PSL, or other formal languages.
• Analyze formal verification results, including counterexamples and traces, and collaborate with design teams to resolve issues.
• Integrate formal methods into the overall verification strategy alongside simulation and emulation.
• Document verification methodologies, results, and best practices.
• Work with EDA tools such as Jasper Gold, Questa Formal, One Spin, or similar.
• Stay updated with the latest advancements in formal methods and apply them to improve verification quality and efficiency.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Solid understanding of digital design principles, including RTL design (Verilog/System Verilog, VHDL).
• Experience with formal verification tools and methodologies.
• Strong knowledge of logic, Boolean algebra, and formal specification languages.
• Familiarity with common bus protocols and microarchitecture concepts.

Non UK nationals are welcome to apply. Visa sponsorship and relocation will be supported for the successful applicant if coming from overseas.

Seniority level:
Mid-Senior level

Employment type:

Full-time

Location:

Oxford, England, United Kingdom