Verification Lead

We are looking for a Senior Verification Engineer to verify high-speed connectivity IP using UVM and advanced System Verilog verification methodologies. The role focuses on functional coverage closure, constrained-random testing, and integration of verification IP (VIP) for next-generation networking protocols.

• Develop and maintain UVM-based verification environments
• Perform constrained-random verification and coverage closure
• Integrate and customize VIP for high-speed interfaces
• Verify protocols including 100
  
  Gb Ethernet, PCIe Gen5, and AMBA/AXI
• Automate verification flows using Python and CI/CD pipelines
• Collaborate with design and software teams; support bring-up using Vivado/Vitis

• Strong UVM and System Verilog verification experience
• High-speed protocol knowledge: 100
  
  GbE, PCIe Gen5, AXI
• Python scripting and Git-based workflows
• Experience with CI/CD in verification environments