Senior Principal Engineer, SerDes Transmitter

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

We are building a world-class Ser Des engineering team to enable next-generation connectivity for AI data centers and high-performance computing.

We are seeking a highly accomplished Senior Principal Engineer to lead the design and development of advanced Ser Des transmitter circuits. This role will drive key transmitter technologies spanning clock generation and distribution, high-speed DACs, output drivers, and innovative circuit techniques for extending bandwidth and improving power efficiency.

The ideal candidate combines deep expertise in high-speed analog and mixed-signal circuit design with hands-on experience in advanced transmitter architectures, time-interleaved DACs, high-speed clocking, and electromagnetic analysis. You will own critical design blocks from architecture and circuit development through layout collaboration, tape-out, and silicon validation, working closely with cross-functional teams to deliver leading-edge high-speed interconnect technology.

Responsibilities:

• Transmitter Design Leadership: Lead the architecture, design, and implementation of high-speed Ser Des transmitter circuits targeting the next-generation high-speed interconnects, with a focus on performance, power efficiency, and silicon robustness.
• Clocking Architecture: Drive transmitter clock generation, distribution, and timing optimization, including multiphase clocking, phase alignment, jitter management, and clock-to-data timing.
• High-Speed DAC Development: Lead the design and optimization of high-speed DACs, including time-interleaved architectures, high-speed switching networks, linearity optimization, and power-efficient implementations.
• DAC Calibration: Develop and optimize calibration techniques for high-speed time-interleaved DACs, addressing timing skew, gain and offset mismatch, nonlinearities, interleaving spurs, and process-voltage-temperature variations.
• Output Driver Design: Lead the design of high-speed output drivers using both current-mode and voltage-mode architectures, optimizing output swing, impedance matching, linearity, power consumption, and signal integrity.
• Bandwidth Extension Techniques: Develop advanced circuit techniques using passive elements and networks—including inductive peaking, impedance shaping, and other bandwidth-extension methods to achieve the required high-frequency performance.
• Electromagnetic Analysis: Apply electromagnetic simulation and extraction tools, such as Cadence EMX, Ansys HFSS, or other EM tools, to analyze and optimize passive structures, interconnects, coupling, and high-frequency circuit behavior.
• Cross-Functional Integration: Collaborate with receiver, clocking, AMS layout, package, signal integrity, and silicon validation teams to optimize end-to-end link performance.
• Silicon Execution: Drive circuit simulations, design reviews, physical implementation, tape-out readiness, silicon characterization, and performance correlation to ensure…