Senior Director, SerDes Digital Design

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.
We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.
If you're looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

We are building a world-class Ser Des engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing. We are seeking an experienced Senior Director of Ser Des Digital Design to lead the architecture, development, and implementation of the digital subsystem for next-generation Ser Des technologies.
The Ser Des digital subsystem plays a critical role in overall PHY performance, supporting digital signal processing (DSP) and equalization, performance calibration, PHY initialization and adaptation, and control and monitoring functions. The successful candidate will bring proven experience delivering digital functionality for 100G+ per-lane Ser Des, combined with the technical depth and leadership skills needed to drive complex, power-efficient, and high-performance silicon.
In this role, you will work closely with DSP, analog, system architecture, verification, and silicon validation teams to define digital architecture and deliver robust, production-quality Ser Des solutions. You will also build and develop a strong engineering organization capable of delivering the digital technologies required for future generations of high-speed connectivity.

• Ser Des Digital Architecture:
  Define and drive the digital architecture for next-generation Ser Des PHYs, aligning DSP, calibration, initialization, adaptation, and control functions with overall system performance requirements
• DSP and Signal Equalization:
  Lead the development and integration of digital signal processing functions supporting high-speed link performance, including transmit and receive equalization, adaptation algorithms, and related datapath processing
• Analog and Mixed-Signal Calibration:
  Drive digital architecture and implementation for analog calibration and compensation, including calibration sequencing, control algorithms, coefficient management, and background or foreground calibration mechanisms
• PHY Initialization and Adaptation:
  Own digital initialization, configuration, training, adaptation, and control sequences required to bring up and maintain robust high-speed links across process, voltage, temperature, and channel variations
• Digital Verification and Quality:
  Establish rigorous design and verification practices to ensure functional correctness, robust corner-case handling, and predictable integration and silicon bring-up
• Cross-Functional Integration:
  Partner closely with analog, receiver, transmitter, clocking, system architecture, firmware, and silicon validation teams to deliver a cohesive end-to-end Ser Des solution
• Silicon Bring-Up and Debug:
  Lead…