×
Register Here to Apply for Jobs or Post Jobs. X

Sr. ASIC​/FPGA Design Verification Engineer; Compute Test Division; North Reading, MA

Job in North Reading, Middlesex County, Massachusetts, 01864, USA
Listing for: Teradyne
Full Time position
Listed on 2026-01-02
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 150800 - 241300 USD Yearly USD 150800.00 241300.00 YEAR
Job Description & How to Apply Below
Position: Sr. ASIC/FPGA Design Verification Engineer (Compute Test Division; North Reading, MA)

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Our Logic Design Engineering team is seeking a digital logic Verification Engineer who preferably also has experience in FPGA design.

  • The primary focus of the role will be FPGA verification including:
    • Review of design requirements documents
    • Writing and reviewing verification plans
    • Testbench architecture and implementation
    • Reference model development
    • Test writing and debug
    • Functional/code coverage collection, merging and closure
    • Managing bugs/issues in a bug tracking tool
    • Collaboration with logic designers, board designers and software designers
    • Communicating status to project leadership
All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • BS/MS (or higher) in Electrical/Computer Engineering or similar technical field
  • Minimum of 10+ years of industry experience
  • Knowledgeable in digital logic verification, preferably using System Verilog & Universal Verification Methodology (UVM)
  • Familiarity with PCIe, Ethernet, AXI, DDRx, I2C, SPI
  • Familiarity with scripting language such as Python, TCL and Perl
  • Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities
  • Excellent written and oral communication skills
  • Familiarity with a digital simulation tool such as Synopsys, Cadence, or Mentor
  • Familiarity with bug/issue tracking tools like JIRA
  • Familiarity with C/C++
  • Familiarity in the use of a source control tools
  • Familiarity working in a Linux based development environment
Preferred
  • Experience with the Cadence Xcelium simulation tool.
  • Experience with the digital logic verification using System Verilog & Universal Verification Methodology (UVM)
  • Experience in logic design writing RTL in Verilog HDL
  • Experience with physical design tools from FPGA vendors (Vivado and/or Quartus)
  • Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)
  • Experience with continuous integration/continuous development (CI/CD) development flows
Compensation

The base salary range for this role is $150,. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please  to see details.

#J-18808-Ljbffr
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
 
 
 
Search for further Jobs Here:
(Try combinations for better Results! Or enter less keywords for broader Results)
Location
Increase/decrease your Search Radius (miles)

Job Posting Language
Employment Category
Education (minimum level)
Filters
Education Level
Experience Level (years)
Posted in last:
Salary