Senior ASIC Verification Engineer - SystemVerilog​/UVM

Teradyne in North Reading, MA seeks an ASIC Verification Engineer to join the Reference Model team. You will verify complex ASIC/SoC designs using SystemC, System Verilog/UVM, and constrained-random methods, collaborating with design, firmware, and software groups.

The role emphasizes verification planning, testbench architecture, and delivering high-quality results with rigorous methodologies. Bachelor’s degree required;
Master’s preferred, with 4+ years in semiconductor verification.

We are looking to fill the Senior ASIC Verification Engineer
- System Verilog/UVM position at Teradyne in North Reading, MA, United States.

Learn more about the Senior ASIC Verification Engineer
- System Verilog/UVM role in the description above.

We appreciate your interest in this position.

Join Teradyne and contribute to our ongoing work.

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This posting is for the Senior ASIC Verification Engineer
- System Verilog/UVM role at Teradyne, based in North Reading, MA, United States.