Advanced ASIC Physical Design Lead; Teradyne, North Reading, MA)

Position: Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview Teradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to Teradyne’s next-generation SoC and memory test  this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads.

You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.

What You’ll DoLead and mentor a team of physical design engineers across the full project lifecycle

Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects

Develop and own chip floor plans, timing budgets, power estimates, and pin planning

Partner with design teams to develop high-quality SDC constraints

Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
Support hands-on place-and-route (P&R) for critical and high-speed blocks

Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals

Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and Ser Des Ensure  robust signoff closure including DRC/LVS and EM/IR analysis

Develop, enhance, and maintain physical design tool flows and automation

All About You We seek individuals who share our passion and determination.

Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.
10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects

Proven experience at advanced technology nodes (16nm and below)
Deep expertise in RTL-to-GDSII flows and timing closure

Strong understanding of STA, constraints development, and signoff methodologies

Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, Ser Des)
Proficiency with industry-standard EDA tools (Cadence preferred)
Strong scripting and automation skills using Tcl, Python, and/or Make Ability to lead technically, communicate clearly, and collaborate across disciplinesBS or MS in Electrical…