Hardware​/Software Integration Engineer; Compute Test, North Reading

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Date: Sep 10, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Semiconductor test instruments span a deep vertical stack: application software on a host PC, an instrument driver and API layer, embedded software running on module-level processors, a hardware abstraction layer, FPGA logic, and finally the ASICs and DACs that put real volts and amps on a device under test.

Most engineers own one or two of those layers. This role owns the seams between all of them.

You will be the engineer who can start from “the test program asked for X and the pin did Y” and trace the full chain, including API call, driver layer, register write, FPGA logic, DAC code, and output voltage, until you isolate the layer where behavior diverges from intent. You will read code, RTL, and schematics beyond your own deliverables. You will find defects in a new board's software stack before the board arrives.

And you will bring logic design, FPGA, and software engineering into the same conversation and keep them aligned until the issue is closed.

• Trace and root-cause defects end to end across the instrument stack, from host application and driver API through embedded software, the hardware abstraction layer, FPGA and ASIC/DAC programming, and drive the fix in whichever layer owns it.
• Own the correctness of translation layers, including API surfaces and enumerations, register maps, bitstream encodings, and calibration math that converts engineering units into DAC codes and back.
• Review code, HDL and schematics beyond your own deliverables, including abstraction-layer source, FPGA logic, register map changes across board revisions, and power-on versus runtime initialization paths.
• De-risk new board revisions before hardware arrives by reviewing initialization, connect/disconnect pathways, and break-before-make sequencing.
• Build and improve debug tooling, instrumentation, unified timeline views, automated analysis workflows, and AI-assisted debug and log review capabilities.
• Support internal diagnostic, calibration, continuity, and production verification paths alongside customer-facing APIs.
• Align logic design, FPGA, embedded software, and applications teams around shared failure models and maintain knowledge-sharing documentation.
• Work backward from customer use cases to verify end-to-end system behavior across the stack.
• Set technical direction for cross-layer…