Memory Layout Engineer

Tasks will include performing full Custom Layout Design for MRAM, designing layouts of various blocks, and performing Chip Level verifications after tiling them as a single memory instance.

Specific responsibilities include:

• Layout Design for various memory blocks such as Row decoder, Control, Sense Amplifier, etc.
• Tiling blocks to create a single memory instance and performing Layout verifications.
• CHIP Level verification and signoff after making connections to the PAD.

The ideal candidate will have:

• A minimum of 6+ years of experience in a similar position.
• A strong knowledge of Memory layout fundamentals and experience in designing layouts for deep submicron technologies.
• The ability to perform all verifications like DRC, LVS, etc. and perform Full CHIP signoff.
• Some experience in designing SRAM would be an advantage.
• Some prior knowledge of SKILL coding would be an advantage.
• Experience in preparing reports.