ASIC Design Engineer

Trusted Semiconductor Solutions provides integrated circuit development services from concept to qualified part delivery leveraging the best-in-class on-shore manufacturing capabilities. Trusted Semiconductor Solutions specializes in IC design and high-density package solutions with expertise in radiation hardening for space and strategic applications. Trusted Semiconductor Solutions is a Trusted accredited supplier and a non-traditional defense contractor. For more information, please visit:  .

Trusted Semiconductor Solutions has an immediate opening for an ASIC Design Engineer I.

Please Note:

Applicants must be a U.S. Citizen,U.S. Permanent Resident, Political Asylee, or Refugee to be considered for this position.

As a Digital Design Engineer I, you will take ownership of the full chip development from architecture definition through release to production. The right candidate will be someone with high aptitude who is currently hands on designing complex digital blocks, with strong knowledge/experience across the complete ASIC/SOC design flow. An ideal candidate will additionally have experience with radiation-hardened design, analog/mixed-signal design and EDA, and std-cell library development.

The candidate is expected to design and verify circuits, logic, systems, and algorithms to meet product requirements. The individual will determine the proper method and procedures to be used in the digital system development and determine the best method for verifying the digital system before the complete design is committed to silicon. Candidate must have experience in implementing the proposed method and procedure to design and verify ASIC digital circuits.

• Design and implement digital circuits using industry-standard EDA tools (such as Cadence or Synopsys).
• Develop RTL (Register Transfer Level) designs for complex digital blocks.
• Optimize power, area, and performance trade-offs.

• Conduct functional and timing simulations to validate circuit behavior.
• Collaborate with verification engineers to create test benches and perform RTL simulations.
• Ensure compliance with design specifications and standards.

• Analyze critical paths, setup/hold times, and clock domain crossings.
• Optimize circuit performance through gate-level simulations and static timing analysis.
• Investigate and resolve design issues related to power consumption and signal integrity.
• Work closely with layout engineers to ensure proper physical implementation.
• Collaborate with system architects to define digital subsystem requirements.
• Participate in design reviews and contribute innovative ideas.

• Create and maintain design documentation, including specifications, block diagrams, and design constraints.
• Assist in generating production drawings and assembly procedures.

• Bachelors/Masters in Electronic Engineering/Computer Science or equivalent.
• Entry level experience with ASIC and/or SoC design.
• A strong background in RTL based digital IC design using Verilog/System Verilog.
• Proven track record of first-pass successes.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Experience with industry standard development tools and methodologies.
• The US base salary range for this full-time position is $74,000 – $100,000

• Work at the TSS office in Brooklyn Park, MN is strongly preferred. Willing to consider remote work.