Remote Senior SoC Verification Engineer – UVM​/SystemVerilog

An innovative firm is seeking a Senior SoC Design Verification Engineer to join their remote team. In this role, you will leverage your extensive experience in functional verification of complex SoCs, utilizing UVM and System Verilog. You will be responsible for developing test plans, creating test benches, and collaborating with a skilled team to ensure design integrity through rigorous testing and debugging.

This position offers an exciting opportunity to lead technical projects and mentor junior engineers, contributing to cutting-edge methodologies in a dynamic work environment. If you are passionate about SoC design and verification, this role is perfect for you.
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