Remote Senior SoC Verification Engineer – UVM​/SystemVerilog

An innovative firm is seeking a Senior SoC Design Verification Engineer to join their remote team. This role involves functional verification of complex SoCs using UVM and System Verilog, collaborating with a skilled team to develop test plans, write test benches, and debug designs. The ideal candidate will have extensive experience in SoC verification and be proficient in various programming languages.

This position offers a unique opportunity to contribute to cutting-edge projects while enjoying a comprehensive benefits package, including stock options and a 401k plan. If you are passionate about technology and looking to make a significant impact, this role is for you.
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