Senior Physical Design​/Layout Engineer

Ser Des / Analog Mixed‑Signal IC Design Engineer

About Us

StarIC is a Toronto‑based semiconductor design company focusing on analog and mixed‑signal design where precision meets innovation.

Why StarIC?

• Exciting projects that redefine the industry
• Continuous learning culture and opportunities to teach others
• Global impact through advanced mixed‑signal ICs
• Collaboration with layout, digital, and system teams
• Client engagement via discussions and presentations

Qualifications We’re Seeking

• Education:
  
  Master’s or PhD in Electrical Engineering with focus on IC design
• Experience:
  
  3+ years in IC design, including CTLE, DFE, ADC, DAC, oscillators, PLLs
• Ser Des / High‑Speed design (>10 GS/s) a significant asset
• Multiple silicon designs taped out with measured results
• Experience with SOI or FinFET process nodes a plus
• Proficiency in scripting, programming and tools such as MATLAB/Simulink and Python
• Strong communication, presentation skills and teamwork
• Eligible to work in Canada

Perks And Benefits

• Competitive compensation
• Positive work environment in a growing company
• Hybrid work arrangement
• Only applicants with multiple IC tape‑outs considered

Key Responsibilities

• Lead and manage digital development and design projects
• Oversee all phases of digital block and IC development from concept through final verification
• Handle specification, modeling, RTL, verification, synthesis, timing closure, simulation, lab testing, layout support, and documentation
• Execute incremental updates and maintenance of existing digital designs, test systems, and supporting tools
• Conduct design reviews, contribute to characterization and qualification test systems, support backend design targeting silicon, FPGAs, and system simulators

Qualifications

• BSc or MSc in Electronic or Computer Engineering
• 3–6 years of digital IC design experience (academic experience considered)
• Experience in VHDL and/or Verilog design and simulation
• Front‑end tool experience (Synopsys, Cadence, Mentor) including verification, synthesis, STA, gate‑level simulation
• Backend tools and flow experience; ability to coordinate with backend team
• Knowledge of DSP algorithms and building blocks a plus
• Hands‑on scripting experience (csh, Tcl/Tk, Perl)
• Ability to work with global, cross‑functional teams
• Project management skills a plus
• Strong analytical, debugging and independent work capabilities
• Excellent English communication skills

Perks And Benefits

• Competitive compensation
• Great work environment
• Hybrid work eligibility
• Only applicants with multiple IC tape‑outs considered

The Role

Work on state‑of‑the‑art TIA and Driver designs for silicon photonics at very high speeds, integrating active circuits with photonics elements into high‑speed electro‑optical systems. Lead design development and sign‑off.

Qualifications We’re Seeking

• Education:
  
  Master’s or PhD in Electrical Engineering focused on IC design
• 3+ years of design experience, including optical front‑end receivers/transmitters (TIAs, Drivers), CTLE, DFE, ADC, DAC, oscillators, PLLs
• Experience with photonics elements (PD, MRM, MZ) a significant asset
• Ser Des / High‑Speed design (>10 GS/s) a significant asset
• Multiple silicon designs taped out with measured results
• Experience with EIC/PIC co‑design and co‑simulation of photonics and electronics a plus
• SOI or FinFET node experience a plus
• Proficiency in MATLAB/Simulink, Python
• Strong communication, presentation skills, teamwork
• Eligible to work in Canada

Perks And Benefits

• Competitive compensation
• Positive work environment
• Hybrid work arrangement
• Only applicants with multiple IC tape‑outs considered

Key Responsibilities

• Develop and conceptualize design layouts for key analog/mixed‑signal designs
• Perform EMIR, DFM, parasitic analysis and optimization
• Collaborate with analog/mixed‑signal and digital designers to ensure optimal layout and floor plans
• Project management and task delegation
• Create and manage scripts for flow optimization
• Contribute to design flow and resource management
• Knowledge transfer and discussions with clients on layout/floorplan requirements

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering
• 3+ years of experience
• Multiple tape‑out experience in advanced technology nodes
• High‑speed layout experience a significant asset
• SOI/FinFET experience a significant asset
• Experience with Cadence design flow
• Strong communication and teamwork skills

Perks And Benefits

• Competitive compensation
• Great work environment
• Hybrid work eligible; remote working available
• Only applicants with multiple IC tape‑outs considered

Contact: – send your resume and join our trailblazing team  look forward to hearing from you.