SMTS Logic Design

Overview

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Member of Technical Staff (SMTS) – Logic Design Engineer to join our PCIe Switch Architecture and Design team in Montreal, Canada. In this role, you will be working with some of the brightest inventors and engineers in the world developing next-generation PCIe Gen6/Gen7 switch products that make data faster and safer.

As a Senior Member of Technical Staff (SMTS) – Logic Design Engineer, you’ll play a pivotal role in PCIe Gen6/Gen7 switch IP development, contributing to architecture definition, micro-architecture development, RTL implementation, and design closure of high-performance ASIC IP. In this full-time role, you’ll report directly to the Logic Design leadership team. Our PCIe Switch Architecture and Design team is dedicated to developing scalable, high-performance switch IP for advanced connectivity solutions, and your contributions will be instrumental in delivering next-generation PCIe switch product milestones.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

The successful candidate will contribute across the full product lifecycle, from architecture and micro-architecture through RTL implementation, verification support, emulation, and design closure.

• Analyze product requirements and contribute to architecture and micro-architecture development for next-generation PCIe Gen6/Gen7 switch products.
• Define and document complex hardware subsystems, including PCIe switch fabric, port controllers, routing and arbitration logic, flow control and credit management, buffer management, power management features, and configuration/register infrastructure.
• Review specifications and identify implementation risks, performance bottlenecks, scalability concerns, and opportunities for design optimization.
• Develop high-quality, synthesizable RTL using System Verilog and design high-performance pipelines capable of supporting PCIe Gen6 and Gen7 data rates.
• Implement timing-conscious and physically-aware architectures suitable for advanced process nodes, ensuring RTL is scalable, reusable, and maintainable.
• Lead the development of significant design blocks independently and drive resolution of complex technical issues spanning architecture, implementation, and verification.
• Mentor junior and intermediate engineers, participate in design reviews, and provide technical guidance across the team.
• Collaborate with verification engineers to define verification strategies, coverage goals, and debug approaches.
• Support block, subsystem, emulation, FPGA, and silicon debug activities, including analysis of protocol, performance, and functional issues discovered during verification or customer engagements.
• Conduct RTL reviews, enforce coding guidelines, and support CDC, RDC, lint, synthesis, and timing closure activities.
• Participate in continuous improvement of design methodologies, automation flows, and development processes.

Candidates should demonstrate strong ASIC/SoC logic design experience, technical leadership, and the ability to deliver complex silicon IP from architecture through tape-out.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline.
• 8+ years of ASIC/SoC logic design experience with proven delivery of complex silicon products from architecture through tape-out.
• Expert knowledge of System Verilog, RTL design methodologies, and ASIC development flows.
• Strong understanding of pipelined architectures, resource arbitration, state machine design, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques.
• Experience with synthesis and timing closure, including industry-standard EDA tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus, Spy Glass, and Questa/Visualizer.
• Preferred: deep knowledge of PCIe Gen5/Gen6/Gen7 protocol architecture and experience designing PCIe switches, root complexes, PCIe endpoints, or…