Analog Mixed-Signal IC Design Engineer; Custom Digital Timing Characterization and Liberty Modeling TeraWave

Application close date:
Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! Blue Origin is pioneering the future of space-based communications with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth.

This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide. We are seeking a Senior-level Mixed-Signal / Custom Digital IC Designer to develop, simulate, characterize, and deliver timing models for custom analog-digital interface circuits. This role is responsible for creating high-quality Liberty .lib timing models and related collateral for custom digital and mixed-signal interface blocks used in complex integrated circuits.

The ideal candidate has strong transistor-level circuit design and simulation experience, deep understanding of digital timing concepts, and hands‑on experience characterizing custom cells or interfaces for setup, hold, clock-to-Q, recovery/removal, pulse-width, propagation delay, slew, load, and PVT variation. This person will work closely with analog designers, digital implementation engineers, STA engineers, verification engineers, and physical design teams to ensure that custom mixed-signal interfaces are accurately represented in digital timing flows.

This role is well suited for a designer who is comfortable operating at the boundary between analog/mixed-signal design, custom digital design, static timing analysis, and library characterization.

• Relocation provided
• Travel expected up to 10% of the time
• Interviews will include a technical assessment
• This role is based on site in San Diego (preferred), CA Or Cupertino, CA; A temporary remote work exception is approved while our San Diego sites are being developed.

• Generate and maintain Liberty .lib models for custom digital and analog-digital interface circuits:
  Define and characterize timing arcs including input-to-output delay, clock-to-Q delay, setup and hold constraints, recovery and removal timing, minimum pulse-width constraints, enable/disable timing, tristate or conditional timing arcs, where applicable.
• Characterize timing over relevant PVT corners, input slew ranges, output load ranges, and extracted parasitic conditions
• Model pin capacitance, transition behavior, leakage, dynamic power, and related Liberty attributes as needed.
• Validate generated .lib files against transistor-level simulation results and downstream STA behavior.
• Ensure .lib compatibility with digital implementation and signoff tools such as Prime Time, Tempus, Innovus, Fusion Compiler, or equivalent.
• Perform SPICE-level characterization:
  Build, debug, and maintain transistor-level simulation test benches for custom interface circuits.
• Run SPICE or FastSPICE simulations using tools such as Spectre, HSPICE, Eldo, Fine Sim, XA, or equivalent.
• Develop measurement methodologies for setup/hold extraction, propagation delay, clock-to-Q delay, transition time, minimum pulse width, recovery/removal checks, and metastability-sensitive timing behavior
• Perform simulation across PVT and parasitic-extracted views.
• Analyze waveform behavior and identify root causes of timing anomalies, non‑monotonicity, race conditions, glitches, contention, or…